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GTL2107
12-bit GTL-/GTL/GTL+ to LVTTL translator
Rev. 05 -- 23 December 2009 Product data sheet
1. General description
The GTL2107 is a customized translator between dual Xeon processors, GTL-/GTL/GTL+ I/O and the Platform Health Management, South Bridge and Power Supply 3.3 V LVTTL and GTL signals.
2. Features
Operates as a GTL to LVTTL sampling receiver or LVTTL to GTL driver Operates at GTL, GTL+ or GTL- levels EN1 and EN2 enable control 3.0 V to 3.6 V operation LVTTL I/O not 5 V tolerant Series termination on the LVTTL outputs of 30 ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 Class II, Level A which exceeds 500 mA Package offered: TSSOP28
3. Quick reference data
Table 1. Quick reference data Tamb = 25 C. Symbol tPLH tPHL Parameter LOW to HIGH propagation delay HIGH to LOW propagation delay Conditions nA to nBI; see Figure 4 nBI to nA or nAO (open-drain outputs); see Figure 13 nA to nBI; see Figure 4 nBI to nA or nAO (open-drain outputs); see Figure 13 nA to nBI; see Figure 4 nBI to nA or nAO (open-drain outputs); see Figure 13 nA to nBI; see Figure 4 nBI to nA or nAO (open-drain outputs); see Figure 13 Min 1 2 2 2 1 2 2 2 Typ 4 13 5.5 4 4 13 5.5 4 Max 8 18 10 10 8 18 10 10 Unit ns ns ns ns ns ns ns ns Vref = 0.73 V; VTT = 1.1 V
Vref = 0.76 V; VTT = 1.2 V tPLH tPHL LOW to HIGH propagation delay HIGH to LOW propagation delay
NXP Semiconductors
GTL2107
12-bit GTL-/GTL/GTL+ to LVTTL translator
4. Ordering information
Table 2. Ordering information Tamb = -40 C to +85 C. Type number Topside mark Package Name TSSOP28 Description plastic thin shrink small outline package; 28 leads; body width 4.4 mm Version SOT361-1
GTL2107PW GTL2107
5. Functional diagram
GTL2107
GTL VREF 1AO LVTTL outputs (open-drain) 2AO 1 2 27 1BI GTL inputs 3 26 2BI
5A LVTTL inputs/outputs (open-drain) 6A LVTTL input EN1
4
&
25
7BO1 GTL outputs
5 6
&
24
7BO2
23 7
EN2
LVTTL input
GTL input
11BI
1
22
11BO
GTL output
LVTTL input/output (open-drain)
11A
8
DELAY(1) 21 5BI
GTL input
9BI
9
DELAY(1) 20 6BI GTL inputs
3AO LVTTL outputs (open-drain) 4AO
10
19
3BI
11
18
4BI
1 10AI1 LVTTL inputs 10AI2 13 12 1
17
10BO1 GTL outputs
16
10BO2
15
9AO
LVTTL output
002aac745
(1) The enable on 7BO1/7BO2 include a delay that prevents the transient condition (where 5BI/6BI go from LOW to HIGH, and the LOW to HIGH on 5A/6A lags up to 100 ns) from causing a LOW glitch on the 7BO1/7BO2 outputs.
Fig 1.
GTL2107_5
Logic diagram of GTL2107
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 23 December 2009
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NXP Semiconductors
GTL2107
12-bit GTL-/GTL/GTL+ to LVTTL translator
6. Pinning information
6.1 Pinning
VREF 1AO 2AO 5A 6A EN1 11BI 11A 9BI
1 2 3 4 5 6 7 8 9
28 VCC 27 1BI 26 2BI 25 7BO1 24 7BO2 23 EN2 22 11BO 21 5BI 20 6BI 19 3BI 18 4BI 17 10BO1 16 10BO2 15 9AO
002aac746
GTL2107PW
3AO 10 4AO 11 10AI1 12 10AI2 13 GND 14
Fig 2.
Pin configuration for TSSOP28
6.2 Pin description
Table 3. Symbol VREF 1AO 2AO 5A 6A EN1 11BI 11A 9BI 3AO 4AO 10AI1 10AI2 GND 9AO 10BO2 10BO1 4BI 3BI
GTL2107_5
Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Description GTL reference voltage data output (LVTTL), open-drain data output (LVTTL), open-drain data input/output (LVTTL), open-drain data input/output (LVTTL), open-drain enable input (LVTTL) data input (GTL) data input/output (LVTTL), open-drain data input (GTL) data output (LVTTL), open-drain data output (LVTTL), open-drain data input (LVTTL) data input (LVTTL) ground (0 V) data output (LVTTL), push-pull data output (GTL) data output (GTL) data input (GTL) data input (GTL)
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Product data sheet
Rev. 05 -- 23 December 2009
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GTL2107
12-bit GTL-/GTL/GTL+ to LVTTL translator
Pin description ...continued Pin 20 21 22 23 24 25 26 27 28 Description data input (GTL) data input (GTL) data output (GTL) enable input (LVTTL) data output (GTL) data output (GTL) data input (GTL) data input (GTL) positive supply voltage
Table 3. Symbol 6BI 5BI 11BO EN2 7BO2 7BO1 2BI 1BI VCC
7. Functional description
Refer to Figure 1 "Logic diagram of GTL2107".
7.1 Function tables
Table 4. Power supervisor power good control H = HIGH voltage level; L = LOW voltage level; X = Don't care. Inputs EN1 H H L 1BI/2BI L H X Output 1AO/2AO (open-drain) L H H
Table 5. Power supervisor power good control H = HIGH voltage level; L = LOW voltage level; X = Don't care. Inputs EN2 H H L 3BI/4BI L H X Output 3AO/4AO (open-drain) L H H
Table 6. Southbridge SMI_L control H = HIGH voltage level; L = LOW voltage level. Input 9BI L H Output 9AO (push-pull) L H
GTL2107_5
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Product data sheet
Rev. 05 -- 23 December 2009
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NXP Semiconductors
GTL2107
12-bit GTL-/GTL/GTL+ to LVTTL translator
Table 7. CPU SMI_L control H = HIGH voltage level; L = LOW voltage level. Inputs 10AI1/10AI2 L L H H 9BI L H L H Output 10BO1/10BO2 L L L H
Table 8. PROCHOT L control H = HIGH voltage level; L = LOW voltage level. Inputs EN2 H H H L L L L
[1]
Input/output 5BI/6BI L H H H H L L 5A/6A (open-drain) L L[2] H L[2] H H L[2]
Output 7BO1/7BO2 H[1] L H L H H H
The enable on 7BO1/7BO2 includes a delay that prevents the transient condition (where 5BI/6BI goes from LOW to HIGH, and the LOW to HIGH on 5A/6A lags up to 100 ns) from causing a low glitch on the 7BO1/7BO2 outputs. Open-drain input/output terminal is driven to logic LOW state by an external driver.
[2]
Table 9. Southbridge NMI control H = HIGH voltage level; L = LOW voltage level. Input 11BI L L H
[1]
Input/output 11A (open-drain) H L[1] L
Output 11BO L H H
Open-drain input/output terminal is driven to logic LOW state by an external driver.
GTL2107_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 23 December 2009
5 of 19
NXP Semiconductors
GTL2107
12-bit GTL-/GTL/GTL+ to LVTTL translator
8. Application design-in information
VTT
56 R 56
VTT
1.5 k to 1.2 k
VCC
2R 1.5 k
PLATFORM HEALTH MANAGEMENT CPU1 1ERR_L CPU1 THRMTRIP L CPU1 PROCHOT L CPU2 PROCHOT L
VCC VREF 1AO 2AO 5A 6A EN1 11BI VCC 1BI 2BI 7BO1 7BO2 EN2 11BO CPU1 IERR_L THRMTRIP L FORCEPR_L PROCHOT L NMI CPU1 SMI_L FORCEPR_L PROCHOT L IERR_L THRMTRIP L NMI CPU2 SMI_L CPU2
GTL2107
NMI_L 11A 9BI CPU2 1ERR_L CPU2 THRMTRIP L CPU1 SMI_L CPU2 SMI_L SMI_BUFF_L 3AO 4AO 10AI1 10AI2 GND 5BI 6BI 3BI 4BI 10BO1 10BO2 9AO
SOUTHBRIDGE NMI SOUTHBRIDGE SMI_L power supervisor POWER GOOD
002aac747
Fig 3.
Typical application
GTL2107_5
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Product data sheet
Rev. 05 -- 23 December 2009
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NXP Semiconductors
GTL2107
12-bit GTL-/GTL/GTL+ to LVTTL translator
9. Limiting values
Table 10. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK VI IOK VO IOL IOH Tstg Tj(max)
[1] [2] [3] [4]
Parameter supply voltage input clamping current input voltage output clamping current output voltage LOW-level output current[2]
Conditions VI < 0 V A port (LVTTL) B port (GTL) VO < 0 V output in OFF or HIGH state; A port output in OFF or HIGH state; B port A port B port A port
[4]
Min -0.5 -0.5[1] -0.5[1] -0.5[1] -0.5[1] -60 -
Max +4.6 -50 +4.6 +4.6 -50 +4.6 +4.6 32 30 -32 +150 +125
Unit V mA V V mA V V mA mA mA C C
HIGH-level output current[3] storage temperature maximum junction temperature
The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. Current into any output in the LOW state. Current into any output in the HIGH state. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C.
10. Recommended operating conditions
Table 11. Symbol VCC VTT Operating conditions Parameter supply voltage termination voltage GTL- GTL GTL+ Vref reference voltage overall GTL- GTL GTL+ VI VIH VIL IOH input voltage HIGH-level input voltage LOW-level input voltage HIGH-level output current A port B port A port and ENn B port A port and ENn B port A port Conditions Min 3.0 0.85 1.14 1.35 0.5 0.5 0.76 0.87 0 0 2 Vref + 0.050 Typ 3.3 0.9 1.2 1.5
2 3VTT
Max 3.6 0.95 1.26 1.65 1.8 0.63 0.84 1.1 3.6 3.6 0.8 Vref - 0.050 -16
Unit V V V V V V V V V V V V V V mA
0.6 0.8 1 3.3 VTT -
GTL2107_5
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Product data sheet
Rev. 05 -- 23 December 2009
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NXP Semiconductors
GTL2107
12-bit GTL-/GTL/GTL+ to LVTTL translator
Table 11. Symbol IOL Tamb
Operating conditions ...continued Parameter LOW-level output current ambient temperature Conditions A port B port operating in free-air Min -40 Typ Max 16 15 +85 Unit mA mA C
11. Static characteristics
Table 12. Static characteristics Recommended operating conditions; voltages are referenced to GND (ground = 0 V). Tamb = -40 C to +85 C. Symbol VOH VOL Parameter HIGH-level output voltage LOW-level output voltage Conditions 9AO; VCC = 3.0 V to 3.6 V; IOH = -100 A 9AO; VCC = 3.0 V; IOH = -16 mA A port; VCC = 3.0 V; IOL = 4 mA A port; VCC = 3.0 V; IOL = 8 mA A port; VCC = 3.0 V; IOL = 16 mA B port; VCC = 3.0 V; IOL = 15 mA IOH II HIGH-level output current input current open-drain outputs; A port other than 9AO; VO = VCC; VCC = 3.6 V A port; VCC = 3.6 V; VI = VCC A port; VCC = 3.6 V; VI = 0 V B port; VCC = 3.6 V; VI = VTT or GND ICC ICC[3] Cio supply current additional supply current input/output capacitance A or B port; VCC = 3.6 V; VI = VCC or GND; IO = 0 mA per input; A port or control inputs; VCC = 3.6 V; VI = VCC - 0.6 V A port; VO = 3.0 V or 0 V B port; VO = VTT or 0 V
[2] [2] [2] [2] [2] [2]
Min VCC - 0.2 2.1 -
Typ[1] 3.0 2.3 0.15 0.3 0.6 0.13 8 5.0 4.0
Max 0.4 0.55 0.8 0.4 1 1 1 1 12 500 -
Unit V V V V V V A A A A mA A pF pF
[1] [2] [3]
All typical values are measured at VCC = 3.3 V and Tamb = 25 C. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. This is the increase in supply current for each input that is at the specified LVTTL voltage level rather than VCC or GND.
GTL2107_5
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Product data sheet
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GTL2107
12-bit GTL-/GTL/GTL+ to LVTTL translator
12. Dynamic characteristics
Table 13. Dynamic characteristics VCC = 3.3 V 0.3 V. Symbol Parameter Vref = 0.73 V; VTT = 1.1 V tPLH LOW to HIGH propagation delay nA to nBI; see Figure 4 9BI to 9AO; see Figure 5 nBI to nA or nAO (open-drain outputs); see Figure 13 9BI to 10BOn 11A to 11BO; see Figure 10 11BI to 11A; see Figure 9 11BI to 11BO 5BI to 7BO1 or 6BI to 7BO2; see Figure 7 tPHL HIGH to LOW propagation delay nA to nBI; see Figure 4 9BI to 9AO; see Figure 5 nBI to nA or nAO (open-drain outputs); see Figure 13 9BI to 10BOn 11A to 11BO; see Figure 10 11BI to 11A; see Figure 9 11BI to 11BO 5BI to 7BO1 or 6BI to 7BO2; see Figure 7 tPLZ LOW to OFF-state propagation delay EN1 to nAO or EN2 to nAO; see Figure 8 EN1 to 5A (I/O) or EN2 to 6A (I/O); see Figure 8 tPZL OFF-state to LOW propagation delay EN1 to nAO or EN2 to nAO; see Figure 8 EN1 to 5A (I/O) or EN2 to 6A (I/O); see Figure 8
[2]
Conditions
Min 1 2 2 2 1 2 2 4 2 2 2 2 1 2 2 100 1 1 1 1
Typ[1] 4 5.5 13 6 4 7.5 8 7 5.5 5.5 4 6 5.5 8.5 14 205 3 3 3 3
Max 8 10 18 11 8 11 13 11 10 10 10 11 10 13 21 350 7 7 7 7
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
GTL2107_5
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Product data sheet
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GTL2107
12-bit GTL-/GTL/GTL+ to LVTTL translator
Table 13. Dynamic characteristics ...continued VCC = 3.3 V 0.3 V. Symbol Parameter Vref = 0.76 V; VTT = 1.2 V tPLH LOW to HIGH propagation delay nA to nBI; see Figure 4 9BI to 9AO; see Figure 5 nBI to nA or nAO (open-drain outputs); see Figure 13 9BI to 10BOn 11A to 11BO; see Figure 10 11BI to 11A; see Figure 9 11BI to 11BO 5BI to 7BO1 or 6BI to 7BO2; see Figure 7 tPHL HIGH to LOW propagation delay nA to nBI; see Figure 4 9BI to 9AO; see Figure 5 nBI to nA or nAO (open-drain outputs); see Figure 13 9BI to 10BOn 11A to 11BO; see Figure 10 11BI to 11A; see Figure 9 11BI to 11BO 5BI to 7BO1 or 6BI to 7BO2; see Figure 7 tPLZ LOW to OFF-state propagation delay EN1 to nAO or EN2 to nAO; see Figure 8 EN1 to 5A (I/O) or EN2 to 6A (I/O); see Figure 8 tPZL OFF-state to LOW propagation delay EN1 to nAO or EN2 to nAO; see Figure 8 EN1 to 5A (I/O) or EN2 to 6A (I/O); see Figure 8
[1] [2] All typical values are at VCC = 3.3 V and Tamb = 25 C. Includes ~7.6 ns RC rise time of test load pull-up on 11A, 1.5 k pull-up and 21 pF load on 11A has about 23 ns RC rise time.
[2]
Conditions
Min 1 2 2 2 1 2 2 4 2 2 2 2 1 2 2 100 1 1 1 1
Typ[1] 4 5.5 13 6 4 7.5 8 7 5.5 5.5 4 6 5.5 8.5 14 205 3 3 3 3
Max 8 10 18 11 8 11 13 11 10 10 10 11 10 13 21 350 7 7 7 7
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
GTL2107_5
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Product data sheet
Rev. 05 -- 23 December 2009
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NXP Semiconductors
GTL2107
12-bit GTL-/GTL/GTL+ to LVTTL translator
12.1 Waveforms
VM = 1.5 V at VCC 3.0 V for A ports; VM = Vref for B ports.
3.0 V input 1.5 V tPLH
VOH VM VM 0V
002aaa999
002aab000
1.5 V 0V tPHL VTT Vref Vref VOL
tp
output
VM = 1.5 V for A port and Vref for B port
A port to B port
a. Pulse duration Fig 4. Voltage waveforms
b. Propagation delay times
VTT input Vref tPLH output 1.5 V Vref
1/ V 3 TT
VTT input Vref tPZL Vref tPLZ
1/ V 3 TT
tPHL VOH 1.5 V VOL
002aab001
VCC output 1.5 V VOL + 0.3 V
002aab002
PRR 10 MHz; Zo = 50 ; tr 2.5 ns; tf 2.5 ns
Fig 5.
Propagation delay, 9BI to 9AO
Fig 6.
nBI to nA (I/O) or nBI to nAO open-drain outputs
3.0 V input 1.5 V tPLZ 1.5 V 0V tPZL VOH output VOL + 0.3 V 1.5 V VOL
002aab005
VTT input Vref tPLH Vref tPHL
1/ V 3 TT
VTT output Vref Vref VOL
002aac195
Fig 7.
5BI to 7BO1 or 6BI to 7BO2
Fig 8.
EN2 to 5A (I/O) or 6A (I/O), or EN1 to nAO, or EN2 to nAO
3.0 V input 1.5 V tPLH 1.5 V 0V tPHL VTT output Vref Vref VOL
002aac197
VTT input Vref tPLZ Vref 0V tPZL VOH output VOL + 0.3 V 1.5 V VOL
002aac196
Fig 9.
11BI to 11A
Fig 10. 11A to 11BO
GTL2107_5
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Product data sheet
Rev. 05 -- 23 December 2009
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GTL2107
12-bit GTL-/GTL/GTL+ to LVTTL translator
13. Test information
VCC PULSE GENERATOR VI DUT
RT CL 50 pF RL 500
VO
002aab981
Fig 11. Load circuit for A outputs (9AO)
VTT VCC PULSE GENERATOR VI DUT
RT CL 30 pF 50
VO
002aab264
Fig 12. Load circuit for B outputs
VCC VCC PULSE GENERATOR VI DUT
RT CL 21 pF RL 1.5 k
VO
002aab265
Fig 13. Load circuit for open-drain LVTTL I/O and open-drain outputs
RL -- Load resistor CL -- Load capacitance; includes jig and probe capacitance RT -- Termination resistance; should be equal to Zo of pulse generators.
GTL2107_5
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Product data sheet
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GTL2107
12-bit GTL-/GTL/GTL+ to LVTTL translator
14. Package outline
TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm SOT361-1
D
E
A
X
c y HE vMA
Z
28
15
Q A2 pin 1 index A1 (A 3) A
Lp L detail X
1
e bp
14
wM
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 9.8 9.6 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.8 0.5 8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT361-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19
Fig 14. Package outline SOT361-1 (TSSOP28)
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Product data sheet
Rev. 05 -- 23 December 2009
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NXP Semiconductors
GTL2107
12-bit GTL-/GTL/GTL+ to LVTTL translator
15. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
15.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
15.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
15.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
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Product data sheet
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GTL2107
12-bit GTL-/GTL/GTL+ to LVTTL translator
15.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 15) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 14 and 15
Table 14. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 15. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 15.
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Product data sheet
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NXP Semiconductors
GTL2107
12-bit GTL-/GTL/GTL+ to LVTTL translator
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 15. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
16. Abbreviations
Table 16. Acronym CDM CPU DUT ESD GTL HBM LVTTL MM PRR Abbreviations Description Charged Device Model Central Processing Unit Device Under Test ElectroStatic Discharge Gunning Transceiver Logic Human Body Model Low Voltage Transistor-Transistor Logic Machine Model Pulse Rate Repetition
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Product data sheet
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12-bit GTL-/GTL/GTL+ to LVTTL translator
17. Revision history
Table 17. Revision history Release date 20091223 Data sheet status Product data sheet 7th Change notice Supersedes GTL2107_4 Document ID GTL2107_5 Modifications:
* * *
Section 2 "Features", bullet item: changed from "200 V MM per JESD22-A115" to "150 V MM per JESD22-A115" Table 1 "Quick reference data": removed symbol/parameter "Cio, input/output capacitance" Table 12 "Static characteristics": - Cio (A port) Typ value changed from "3.0 pF" to "5.0 pF" - Cio (A port) Max value changed from "4.0 pF" to "-" - Cio (B port) Typ value changed from "2.0 pF" to "4.0 pF" - Cio (B port) Max value changed from "3.0 pF" to "-"
*
Table 13 "Dynamic characteristics": - (sub-section Vref = 0.73 V; VTT = 1.1 V) deleted tPHZ specification - (sub-section Vref = 0.73 V; VTT = 1.1 V) deleted tPZH specification - (sub-section Vref = 0.76 V; VTT = 1.2 V) deleted tPHZ specification - (sub-section Vref = 0.76 V; VTT = 1.2 V) deleted tPZH specification
* * *
GTL2107_4 GTL2107_3 GTL2008_GTL2107_2 GTL2008_1
Figure 8 title changed from "EN1 to 5A (I/O) or EN2 to 6A (I/O) or EN1 to nAO or EN2 to nAO" to "EN2 to 5A (I/O) or 6A (I/O), or EN1 to nAO, or EN2 to nAO" Deleted (old) Figure 11 "EN2 to 9AO" Deleted (old) Figure 15 "Load circuit for 9AO OFF-state to LOW and LOW to OFF-state" Product data sheet Objective data sheet Product data sheet Product data sheet GTL2107_3 GTL2008_GTL2107_2 GTL2008_1 -
20070706 20070129 20060926 20060502
GTL2107_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 23 December 2009
17 of 19
NXP Semiconductors
GTL2107
12-bit GTL-/GTL/GTL+ to LVTTL translator
18. Legal information
18.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.
18.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
19. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
GTL2107_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 23 December 2009
18 of 19
NXP Semiconductors
GTL2107
12-bit GTL-/GTL/GTL+ to LVTTL translator
20. Contents
1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 12 12.1 13 14 15 15.1 15.2 15.3 15.4 16 17 18 18.1 18.2 18.3 18.4 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Function tables . . . . . . . . . . . . . . . . . . . . . . . . . 4 Application design-in information . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Recommended operating conditions. . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 8 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Test information . . . . . . . . . . . . . . . . . . . . . . . . 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Soldering of SMD packages . . . . . . . . . . . . . . 14 Introduction to soldering . . . . . . . . . . . . . . . . . 14 Wave and reflow soldering . . . . . . . . . . . . . . . 14 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 14 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 23 December 2009 Document identifier: GTL2107_5

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